The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for internally controlling and enhancing logic built-in self test in a multiple core microprocessor.
A multiple core processor combines two or more independent cores into a single package composed of a single integrated circuit (IC), called a die, or more dies packaged together. For example, a dual-core processor contains two cores, and a quad-core processor contains four cores. A multiple core microprocessor implements multiprocessing in a single physical package. The processors also share the same interconnect to the rest of the system. A system with n cores is effective when it is presented with n or more threads concurrently. Multiple core technology is widely used in many technology areas, especially those of embedded processors, such as network processors and digital signal processors, and in graphical processing units.
With the advent of multiple core processors and on-chip frequency and/or voltage control, new problems and opportunities present themselves. In order to optimize power and performance tradeoffs on multiple core chips during normal operation or runtime, one may wish to adjust on-chip frequency and voltage for each core. Furthermore, to mitigate process yield issues, manufacturers may configure chips with bad cores to operate without the failing core. This means that one must test the functionality and electrical properties of each core independently, which increases the test and characterization time for each chip by a factor of the number of cores on the chip and complicates the manufacturing test procedures.
Logic built-in self test (LBIST) is an important tool in today's microprocessors for isolating critical paths, sorting of frequency, and at AC (at-speed) and DC (stuck-at-fault) logic test coverage. Because LBIST compresses the latches into a multiple input shift register (MISR), it is difficult to determine which latch failed. Typically, software is written for the external testing device to isolate the failing latch using binary searches and the results from a known good device under test from the same device under test at a lower frequency if the fail is a critical path type fail. This latch isolation is extremely time-consuming. An increasing number of processor cores being designed onto a single chip drastically increases this already lengthy test time.